MAX2830
2.4GHz to 2.5GHz 802.11g/b RF Transceiver, PA,
and Rx/Tx/Antenna Diversity Switch
D12 in Register 1 (A3:A0 = 0001) configures the lock-
detect output as a CMOS or open-drain output. In open-
drain output mode, bit D9 in Register 5 (A3:A0 = 0101)
enables or disables an internal 30k ? pullup resistor
from the open-drain output.
Programmable Registers and
3-Wire SPI-Interface
The MAX2830 includes 16 programmable, 18-bit reg-
isters. The 14 most significant bits (MSBs) are used
for register data. The 4 least significant bits (LSBs) of
each register contain the register address. See Table
15 for a summary of the registers and recommended
register settings.
Table 15. Recommended Register Settings*
Register data is loaded through the 3-wire SPI/
MICROWIRE ?-compatible serial interface. Data is
shifted in MSB first and is framed by CS . When CS is
low, the clock is active, and data is shifted with the ris-
ing edge of the clock. When CS transitions high, the
shift register is latched into the register selected by the
contents of the address bits. See Figure 3. Only the last
18 bits shifted into the device are retained in the shift
register. No check is made on the number of clock
pulses. For programming data words less than 14 bits
long, only the required data bits and the address bits
need to be shifted, resulting in faster Rx and Tx gain
control where only the LSBs need to be programmed.
REGISTER
D13
D12
D11
D10
D9
D8
DATA
D7 D6
D5
D4
D3
D2
D1
D0
ADDRESS
(A3:A0)
TABLE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
1
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
0
1
0
0
0
0
0
1
0
0
1
0
1
0
0
0
1
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
0
0
0
0
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
0
1
0
1
0
0
0
0
0
1
0
1
0
1
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
0
1
1
0
1
0
0
1
0
0
0
1
0
1
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
15 0 0 0 0 0 1 0 1 0 0 0 1 0 1
1111 30
*The power-on register settings are not production tested. Recommended register settings must be loaded after V CC is supplied.
DIN
BIT 1
BIT 2
BIT 15
BIT 16
BIT 23
BIT 24
SCLK
t DS
t CL
t CH
t CS1
CS
t CSO
t CSS
t DH
t CSH
t CSW
Figure 3. 3-Wire SPI Serial-Interface Timing Diagram
26
MICROWIRE is a trademark of National Semiconductor Corp.
Maxim Integrated
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